1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the same, and a substrate.
Priority is claimed on Japanese Patent Application No. 2008-136367, filed May 26, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
With higher-performance and higher-speed semiconductor chips, miniaturization of packages has recently been required for multi-terminal packages and high density mounting of semiconductor chips. For example, a BGA (Ball Grid Array)-type semiconductor device is a miniaturized semiconductor device. On one surface of the BGA-type semiconductor device, an area where semiconductor elements are mounted and a wiring pattern to be electrically connected to the semiconductor elements are provided. On the other surface thereof, lands to which solder balls are to be connected are provided in a grid. Thereby, external terminals do not have to be provided on side surfaces thereof as required for QFP (Quad Flat Package)-type semiconductor devices, enabling miniaturization of the mounting area and therefore a mounting substrate. Further, a multi-terminal structure of a package can be implemented with miniaturization of the package.
FIG. 1 is a plane view illustrating an example of a conventional BGA-type semiconductor device 114 viewed from a bump-mounted surface (rear surface). The conventional BGA type semiconductor device 114 includes a bump-free area 118 along the four sides of a substantially rectangular package substrate (wiring substrate) 116, and a bump area 117 provided inside the bump-free area 118.
The bump area 117 is substantially rectangular, inside which circular bumps 120 are aligned in a 6×6 matrix. The bump-free area 118 has a given width from the four sides of the semiconductor device 114, inside which no bump 120 is aligned.
The smaller the bump-free area 118 is, the larger bump area 117 can be provided, and therefore more bumps 120 can be aligned inside the bump area 117, enabling the package substrate 116 to be efficiently used. However, the bump-free area 118 of the conventional BGA-type semiconductor device 114 cannot be reduced in size for the following two reasons.
The first reason is that methods of manufacturing the conventional BGA type semiconductor device use the MAP (Mold Array Package) method, causing problems in a process of manufacturing a semiconductor device if the bump-free area 118 having a given width is not provided.
In the MAP method of manufacturing a semiconductor device, multiple semiconductor chips or bumps are simultaneously mounted on one pre-cut substrate, and then the pre-cut substrate is diced into multiple semiconductor devices. Thereby, simplification of manufacturing processes, enhancement of work efficiency, and a reduction in manufacturing costs can be achieved. For this reason, this method is often used in a manufacturing field.
Respective semiconductor devices are adjacent to one another on the pre-cut substrate. For this reason, if bumps are aligned very close to dicing lines, bumps aligned across the dicing lines are very close to each other, causing the bumps to contact each other or a bridge upon reflowing the bumps. Therefore, a bump-free area having the given size has to be provided.
FIG. 2 is a plane view illustrating an example of a pre-cut substrate 111 viewed from a bump-mounted surface (rear surface) in a conventional MAP.
The pre-cut substrate 111 includes a handling area 113 provided along the four sides of the pre-cut substrate 111 to be used for manufacturing processes, inside which semiconductor devices 114 are aligned in a 3×4 matrix. The pre-cut substrate 111 is diced along the horizontal and vertical dicing lines 112 into 12 pieces of the semiconductor devices 114.
However, respective semiconductor devices 114 are aligned adjacent to one another. If bumps 120 are aligned very close to the dicing lines 112, the bumps 120 aligned across the dicing lines are very close to each other, causing the bumps 120 to contact each other or a bridge upon reflowing the bumps 120. For this reason, bump-free areas 118 having the given size has to be provided.
Thus, the bump-free areas 118 having the given width have to be provided, reducing the areas of bump areas 117 and therefore the number of bumps that can be aligned in the bump areas 17. Consequently, a package substrate 116 cannot efficiently be used. Therefore, a multi-terminal structure and miniaturization of the semiconductor devices 114 cannot be achieved.
The second reason that the bump-free areas 118 are necessary is to prevent land peeling. Generally, lands are provided between bumps and wiring substrate and connected to semiconductor chips through, for example, connection pads.
When the bump-free areas are reduced in size and bumps are aligned very close to the dicing lines, lands corresponding to respective bumps are also aligned very close to the dicing lines. The respective lands are fixed onto the package substrate by being pressed by a solder resist film applied between the bumps and the wiring substrate. However, if the bump-free areas do not have the given size, the effect of pressing by the solder resist film decreases. For this reason, outer lands close to the dicing lines might be peeled when the substrate is diced into pieces of the semiconductor devices. Therefore, the bump-free areas have to have the given width.
To save larger areas for the bump areas, a method of shifting outermost bumps can be considered. For example, Japanese Patent Laid-Open Publication No. 2007-12690 discloses a mounting structure of a BGA-type package.
In this method, outermost bumps are shifted by a half pitch with respect to respective inner bumps. Consequently, the outermost bumps are aligned horizontal to each other across dicing lines on a pre-cut substrate when the MAP method is used. Therefore, the outermost bumps cannot be prevented from contacting each other. Further, a bridge in a reflow process cannot be prevented either.
As a method of preventing land peeling, it can be considered to change the shape of lands. For example, Japanese Patent Laid-Open Publication No. H11-177225 discloses a print substrate on which solder resist clearances provided around respective pads and each having one or more protrusions are provided so that solder flow is restricted by the protrusions upon soldering.
Additionally, Japanese Patent Laid-Open Publication No. 2002-100648 discloses a semiconductor device including circular terminal electrodes with protrusions so that solder follows the protrusions, and consequently the bonding strength between the terminal electrodes and solder bumps increases.
Further, Japanese Patent Laid-Open Publication No. 2000-58700 discloses a BGA-type semiconductor device in which outer pads are rectangular so that solder life can be prolonged. Moreover, Japanese Patent Laid-Open Publication No. 2006-210851 discloses a circuit substrate on which rectangular pads are provided to prevent pad peeling.
However, none of those can prevent outermost lands aligned close to dicing lines from peeling.